The present invention relates to a semiconductor device, and more particularly to a field effect transistor with source/drain diffusion regions having an extremely small capacitance for high speed and high frequency performances.
The most important issue in design of improved field effect transistors such as MOS field effect transistors would be how tzo achieve a possible scaling down and ensure possible high speed and high frequency performances. The field effect transistors such as MOSFETs have been on being subjected to requirements of a scaling down according to the scaling down law. Namely, a scaling down of the MOS field effect transistor requires a certain increase in impurity concentration of source/drain diffusion regions, for which reason the increase in impurity concentration of the source/drain diffusion regions would be unavoidable for improvements of the semiconductor devices including MOS field effect transistors.
On the other hand, high speed and high frequency performances of the field effect transistors such as MOSFETs may largely depend upon an alternating-current capacitance of the source/drain diffusion regions. The capacitance of the source/drain diffusion regions may also depend largely upon a p-n junction capacitance which is generated on an interface of the source/drain diffusion regions to a peripheral semiconductor bulk region in which the source/drain diffusion regions are formed. In the normal field effect transistors such as MOSFETs, the source/drain diffusion regions are formed in a surface region of a semiconductor substrate doped with an impurity at a predetermined impurity concentration or in a well region also doped with an impurity at a predetermined impurity concentration. Impurity concentrations of the semiconductor substrate and the well region should be determined to suppress short channel effects or punch through effects. A magnitude of the p-n junction capacitance depends upon impurity concentrations of the source/drain diffusion regions and the peripheral semiconductor regions such as semiconductor substrate and well region formed in the substrate. Low impurity concentrations of both the source/drain regions and the semiconductor peripheral region such as the semiconductor substrate or the well region may cause a small p-n junction capacitance to be generated at an interface of the source/drain diffusion regions to the semiconductor peripheral region. By contrast, high impurity concentrations of both the source/drain regions and the semiconductor peripheral region such as the semiconductor substrate or the well region may cause a large pn junction capacitance to be generated at an interface of the source/drain diffusion regions to the semiconductor peripheral region. A certain reduction in impurity concentration of at least one of the source/drain diffusion regions and the semiconductor peripheral region such as the semiconductor substrate or the well region may lead to a reduction of the p-n junction capacitance.
From the above descriptions, it would be understood that the scaling down of the field effect transistors such as MOSFETs requires, according to the scaling down law, an increase in impurity concentration of the source/drain diffusion regions and further the increase in impurity concentration of the source/drain diffusion regions may lead to an increase in p-n junction capacitance of the source/drain diffusion regions thereby a capacitance of the source/drain diffusion regions is also increased.
The increased capacitance of the source/drain diffusion regions may, however, render it difficult to allow the field effect transistors to exhibit high speed and high frequency performances, for which reason a reduced or low capacitance of the source/drain diffusion regions is required to allow the field effect transistor to show the required high sped and high frequency performances. According to the scaling down law, it is difficult to reduce the capacitance of the source/drain diffusion regions while the scaling down is required. On the other hand, in view of suppressions of the short channel effects and punch through effects, it is also difficult to largely reduce an impurity concentration of the semiconductor peripheral region such as the semiconductor substrate or the semiconductor well region in which the source/drain diffusion regions are formed.
Under the above circumstances, the scaling down of the field effect transistors such as MOSFETs may prevent the transistors from showing high speed and high frequency performances, for which reasons there have been developed or proposed techniques for reducing the capacitance of the highly doped source/drain diffusion regions.
One of conventional techniques for reducing the capacitance of the source/drain diffusion regions is disclosed in the Japanese Laid-open Patent Application No. 58-2067, which will hereinafter be described with reference to FIGS. 1A and 1B. As illustrated in FIG. 1A, field oxide films 20 are selectively formed in a surface of a p-type semiconductor substrate 10. A gate oxide film 61 is selectively formed at a center of the surface of the p-type semiconductor substrate 10 and then a gate electrode 62 is formed on the gate oxide film 61 to thereby form a gate structure 60. The gate electrode may comprise a polysilicon film having a thickness of 0.5 micrometers and being doped with phosphorus. Arsenic is implanted at an implantation energy of 50 KeV into the surface of the p-type semiconductor substrate 10 by using the gate structure 60 and the field oxide films 20 as masks to form n-type source/drain diffusion regions 90.
As illustrated in FIG. 1B, boron is further implanted at a high implantation energy of 300 KeV into the p-type semiconductor substrate 10 by using the gate structure 60 and the field oxide films 20 as masks to form a p-type high impurity concentration region 100 being positioned at a deep level under the source/drain diffusion regions 90 but positioned just under the gate structure 60 so that a channel region between the source/drain diffusion regions 90 is occupied by the p-type high impurity concentration region 100. This may somewhat contribute to prevent the short channel effects and punch through effect. The p-type high impurity concentration diffusion region 100 is spaced apart from bottoms of the source/drain diffusion regions 90. This may contribute to suppress the unnecessary increase in a p-n junction capacitance of the source/drain diffusion regions.
Another one of the conventional techniques for reducing the capacitance of the source/drain diffusion regions is disclosed in the Japanese Laid-open Patent Application No. 60-94759 will be described with reference to FIG. 2. An n-type low impurity concentration well region 102 is selectively formed in a p-type semiconductor substrate 10 having a low impurity concentration. Field oxide films 20 are selectively formed in a surface of the substrate 10 to separate the n-type low impurity well region 32 from the surface region of the p-type low impurity concentration semiconductor substrate 10. Gate structures 60 comprising gate oxide films 61 and gate electrodes 62 are formed on a surface of the p-type low impurity concentration semiconductor substrate 10 and the n-type low impurity concentration well region 32. Further, n-type and p-type source/drain diffusion regions 54 and 44 are formed in the surface region of the p-type low impurity concentration semiconductor substrate 10 and the n-type low impurity concentration well region 32 respectively. Further, there is formed a p-type high impurity concentration diffusion region 101 having an impurity concentration in the range of from 1.times.10.sup.13 to 6.times.10.sup.13 atoms/cm.sup.3 which is higher than an impurity concentration of the p-type low impurity concentration semiconductor substrate 10 to thereby allow the control of threshold voltage and suppress of punch through phenomenon. An n-type high impurity concentration diffusion region 102 is also formed having a high impurity concentration in the range of from 1.times.10.sup.15 to 3.times.10.sup.15 atoms/cm.sup.3 which is higher than an impurity concentration of the n-type well region 32 to thereby allow the control of threshold voltage and suppress of punch through phenomenon.
The conventional techniques described above for reducing the capacitance of the source/drain diffusion regions would be to use the low impurity concentrations of the semiconductor substrate or the well region in which the source/drain diffusion regions are formed. Indeed, the above conventional techniques have been useful for the conventional devices, however, not applicable to further improved devices to be subjected to a further scaling down. Further scaling down of the device to be required in the future will surely accompany with further increase in impurity concentration of the source/drain diffusion regions, whereas the device will be required to be improved to show further high speed and high frequency performances. Further decrease in impurity concentration of the semiconductor substrate or the well region, in which the source/drain diffusion regions are formed, may cause serious problems with a certain increase in resistance of the substrate and a certain reduction in resistivity to latch-up phenomenon, in addition a certain increase in noise of the substrate. To suppress those problems, it is impossible to further reduce the impurity concentration of the substrate or the well region.
Under the above circumstances, for the purpose of allowing improvements in high speed and high frequency performances of the device, it have been required to develop a quite novel technique for reducing the capacitance of the highly doped source/drain diffusion regions with keeping the necessary high impurity concentration of the substrate and the well region to settle the above problems.